This invention relates to interfacing one or more devices, such as processors, with an external memory via a single bus arbiter.
In order to speed up access to FLASH memory, a page-mode or burst-mode has been developed in which an initial access incorporates multiple consecutive memory address codes so as to read out a block of data into a register which is then accessed incrementally in subsequent accesses until all of the data has been accessed, at which time, the process can be repeated. The advantage of the burst-mode is that each subsequent access can be much short than the initial access, typically, 30 nS for 16 bits compared with 70 nS for initially accessing a block of 128 bits. Burst-mode access is illustrated in FIG. 1 in which an initial access has an address code N and subsequent accesses have address codes N+1, N+2 and N+3. This data burst is ten followed by a second data burst with address codes in the range M.
Burst-mode access makes use of the fact that a processor executes code in a linear fashion to produce consecutive address codes so that once submitted in an initial access, this need not be repeated in subsequent accesses, which can therefore be shorter. However it follows that if the processor does not access all of the data in subsequent accesses, perhaps because it instead requires data at other addresses, then the benefit of fast access is reduced because of more frequent longer initial accesses.
Furthermore sharing of a FLASH memory burst-mode access between multiple processors presents problems which make its use impractical in some circumstances. Thus, for example, multiple embedded processors in an ASIC would beneficially access a single external FLASH memory via a single bus arbiter which determines priority of access between the processors. The use of a single FLASH memory rather than multiple memories, reduces cost, and the number of pins required at the interface connection between the ASIC and memory is kept to a minimum. However, if burst-mode access is used for one or more of the processors, and the benefit is to be maximised by preventing interruption of a burst by other processors, then the latency of access of other processors is increased. There is therefore a compromise between the effective use of burst-mode access by one processor and the latency of access suffered by others. This is exacerbated when individual processors require a higher priority of access, and disrupt burst-mode access by other processors, without necessarily using the burst-mode access themselves. This problem becomes worse if higher priority processors are also required to run at a higher effective MIPS rate.
FIG. 2 illustrates burst-mode access by a first processor over an address range N which is interrupted by higher priority accesses from a second processor over an address range M. The initial access N is followed by a subsequent access N+1, but before subsequent accesses in the address range N can be completed, access is given to the higher priority access M for the second processor. Once this access is completed, access is restored for the first processor, but this has to start again with a longer initial access N+2 before a subsequent access N+3 is completed the second processor then again interrupts with an access M+1 because of its higher priority, before access is again restored to the first processor with N+4 and N+5. Effective use of the burst-mode for the address range N is therefore frustrated by the accesses for the higher priority address range M, and the address range M cannot itself make use of the burst-mode, even though the address codes M and M+1 are consecutive addresses. The average data throughput is therefore severely compromised, approaching the worst case of maxim access time for every access from every processor.